Appeal No. 1997-4115 Page 9
Application No. 08/325,765
encompassed under the logic circuits discussed.” (Id.) He
“points to Column 3 (line 3) - column 4 (line 56),” (id.), of
the reference to support his allegation.
“A rejection based on section 103 clearly must rest on a
factual basis ....” In re Warner, 379 F.2d 1011, 1017, 154
USPQ 173, 178 (CCPA 1967). “The Patent Office has the initial
duty of supplying the factual basis for its rejection. It may
not ... resort to speculation, unfounded assumptions[,] or
hindsight reconstruction to supply deficiencies in its factual
basis.” Id., 154 USPQ at 178. Here, the cited passage is
ambiguous at best. By itself, the passage possibly could be
interpreted as implying the generation of some type of flip-
flop. The examiner shows no basis, however, for interpreting
the passage as teaching the generation, for each output of an
FSM, of an output flip-flop that stores the output. Such an
interpretation amounts to speculation or an unfounded
assumption. We also note the examiner’s admission that
“Chandra did not explicitly give details about including,
within the compilation means, assigning means for assigning
values to unspecified output values so that each state can be
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