Appeal No. 1997-4127 Page 3
Application No. 08/044,241
boot code; the flash EPROM, remaining boot code. A selector
couples a microprocessor to the enable inputs of the OTP ROM
and flash EPROM. When a cycle is executed to the primary boot
code, the OTP ROM is enabled and the flash EPROM is disabled.
When a cycle is executed to the remaining boot code, the flash
ROM is enabled and the OTP ROM is disabled.
Claim 15, which is representative for our purposes,
follows:
15. A computer system, comprising:
a bus;
a microprocessor for asserting cycles on
said bus;
a system ROM coupled to said bus for
storing boot code including primary boot code for
execution by said microprocessor upon power up of
the computer system, other boot code and other
system code, said system ROM comprising:
a flash EPROM coupled to said bus and
having an enable input, said flash EPROM for storing
said other boot code and said other system code; and
a ROM coupled to said bus and having
an enable input, said ROM for storing said primary
boot code; and
a selector coupled to said microprocessor,
said system ROM and said bus, said selector
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