Appeal No. 1998-0662
Application No. 08/561,223
With respect to claims 5 and 13, the Examiner asserts
that Masumori teaches each row is addressed independently
(answer-page 6). Be that as it may, claim 5 recites the
second row address is dependent upon receiving the first row
address. With respect to claim 13, the adjacent rows are
addressed in succession. The Examiner has not shown these
limitations to be taught in the applied references by stating
Masumori addresses each row independently. Thus we will not
sustain the Examiner’s rejection as to these claims.
With respect to claim 6, the Examiner does not address
the requirement that adjacent lines are addressed by ignoring
the least significant bit (answer-page 9). Thus we agree with
Appellants (brief-page 6) that this limitation is not shown by
the combination of references. Accordingly we will not
sustain the Examiner’s rejection of this claim.
With regard to claims 10 and 16, the Examiner does not
address the requirement of delivering a reset signal. Thus we
agree with Appellants that this requirement is not met by the
combination of applied references (brief-pages 7 and 8).
Accordingly we will not sustain the Examiner’s rejection of
these claims.
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