Appeal No. 1998-1107 Page 6
Application No. 08/536,768
from a series combination of delay stages to form a sum."
(Appeal Br. at 20.) He adds, "[n]one of the delay circuits
disclosed by Stehlik (shown as registers in the drawings, for
example elements 172, 176, 178, 182, and 212) have the signals
at a plurality of nodes summed together." (Id. at 21.) The
examiner replies, "the adders included in the integrator cell
circuits in Fig.'s 5B and 5C of Stehlik can also combine a
select group of the true signals from a series combination of
the delay stages to form a sum." (Examiner's Answer at 9.)
Claim 6 specifies in pertinent part the following
limitations:
a) delaying said bitstream signal in a
plurality of serially connected delay stages;
b) summing together the true or complement of
a selected group of said delay stages to form a
summed signal, said group being greater than two
....
Similarly, claim 7 specifies in pertinent part the following
limitations: "delaying said bit stream signal in a plurality
of serially connected delay stages ...." Also similarly,
claims
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