Appeal No. 1998-1107 Page 9
Application No. 08/536,768
Accordingly, claims 6-30 require summing true or complement
signals of selected nodes of a delay circuit. Claims 6-25,
29, and 30 further require that the delay circuit comprises a
serial connection of delay stages.
The examiner fails to show a teaching or suggestion of
the claimed limitations in the prior art. “The Patent Office
has the initial duty of supplying the factual basis for its
rejection. It may not ... resort to speculation, unfounded
assumptions or hindsight reconstruction to supply deficiencies
in its factual basis.” In re Warner, 379 F.2d 1011, 1017, 154
USPQ 173, 178 (CCPA 1967).
Here, the examiner fails to map the exact and complete
language of the claims to the teachings or suggestions of the
references. Instead he broadly observes, "Stehlik uses
Hogenaur filters comprising a plurality of delay stages,
adders, inverters, and integrators (see Fig.'s 5A-C and col.
7, lines
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