Appeal No. 1998-1107 Page 10
Application No. 08/536,768
21-67)." (Examiner's Answer at 9.) The reference teaches a
decimation filter stage comprising myriad components.
Specifically, Stehlik includes the following description.
The first decimation filter stage 124, 126 is
illustrated in FIG. 5A. Each filter 124, 126
includes a cascaded integrator filter section 170
having a number of integrator cells 171; a first
register 172 following the cascaded integrator
filter section 170; a cascaded comb filter section
173 having a number of comb cells 174; and a second
register 176 following the cascaded comb filter
section 173.
Col. 7, ll. 39-45. The examiner fails to explain, however,
which of these components he believes constitutes a delay
circuit comprising a serial connection of delay stages.
The examiner's reply that "the adders included in the
integrator cell circuits in Fig.'s 5B and 5C of Stehlik can
also combine a select group of the true signal from a series
combination of the delay stages to form a sum," (Examiner's
Answer at 9), is also inexact. Stehlik teaches an integrator
cell comprising plural components and connections.
Specifically, Stehlik includes the following description.
An example of an integrator cell 171 is shown in
FIG. 5B and includes a register 178 and an adder
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