Appeal No. 1998-1107 Page 8
Application No. 08/536,768
complementary signals derived from the nodes of said
series connection of delay stages are combined
together in a combination circuit to provide a
summed signal ....
Further similarly, claims 15-21 each specifies in pertinent
part the following limitations:
a series connection of delay stages having an input
terminal for receiving an input signal and an output
terminal, wherein a select group of the true and
complementary signals derived from the nodes of said
series connection of delay stages are summed
together to provide a summed signal ....
Similarly, claims 22-25, 29, and 30 each specifies in
pertinent part the following limitations:
a) a plurality of serially connected delay
stages having an input terminal for receiving an
input signal;
b) a means for detecting the state of signals
at selected nodes of said serially connected delay
stages and for generating a sum signal which
corresponds to the sum of one of the true or
complement signals present at said selected nodes
....
Also, claims 26-28 each specifies in pertinent part the
following limitations:
the steps of integrating, summing, delaying, and
decimating a data bit stream, wherein said summing
step comprises summing one of the true or complement
signals at a selected plurality of nodes of a delay
circuit used to perform the delaying step ....
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