Appeal No. 1998-1319
Application No. 08/466,188
output to the matrix display has a constant voltage level
during a horizontal scanning period, as determined above.
In addition, Aoki explains (column 3, lines 13-16) that
the A/D converter converts the video signal into a 4-bit
digital signal. The voltage generator outputs voltages V -V ,
0 5
or 6 voltage levels (see column 3, lines 58-62), and 16
gradation levels (or 2 gradations) are formed by combinations4
of the 6 voltages (see figure 5). Claims 20 through 22, 31,
33, 38, and 43 recite that the number of voltage levels
generated is 2 , where N equals the number of bits ofN
information. Since the number of bits in Aoki is 4, 2 equals4
16, the number of voltages is 6, and 6 is not 16, Aoki does
not meet the claimed limitation. Accordingly, we must reverse
the rejection of claims 20 through 22, 31, 33, 38, and 43 over
Aoki.
Claims 24 through 27 include a timing correction circuit
for correcting a phase deviation between the serial digital
display data and the parallel digital display data. We find
no such circuit in Aoki, and the examiner has failed to point
to any specific structure to meet this limitation. Further,
the examiner has failed to explain or provide any evidence
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