Appeal No. 1998-1510
Application No. 08/205,737
(iv)(c) not invalidating said at least one cache line if
said read data does not correspond to the highest address word
in said at least one cache line.
The examiner relies on the following references:
Chang et al. (Chang) 4,197,580 Apr. 8,
1980
Baum et al. (Baum) 4,928,239 May 22,
1990
Intel, “386™ DX Microprocessor Programmer’s Reference Manual”
(1991).
Claims 1 through 5 stand rejected under 35 U.S.C. § 103
as unpatentable over Intel in view of Baum.
Reference is made to the briefs and answer for the
respective positions of appellants and the examiner.
OPINION
Claims 1 through 5 will stand or fall together, as
indicated by appellants at page 6 of the principal brief.
Accordingly, we will limit our consideration to the rejection
of independent claim 1.
The examiner’s position is that Intel discloses the
claimed subject matter except that the cache used by Intel
does not invalidate the line if the word being referenced in
the cache line is the highest addressed. The examiner then
relies on Baum for the teaching of invalidating a line in a
cache when a POP instruction has been issued and that POP
3
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