Appeal No. 1998-1510
Application No. 08/205,737
as an appendix to the answer, that while step (iv)(b) of
instant claim 1 is not actually taught by Intel or Baum, this
claimed step is “believed to be one of logical reasoning
and/or common sense.” Basically, the examiner shows why
certain operations would result in inefficiencies and then
concludes [answer-page 7] that the “most obvious way” of
eliminating those inefficiencies would be “to not load the
entire cache line into the cache.” While a claimed invention
may seem simple and merely the result of “logical reasoning
and/or common sense” in retrospect, i.e., after an applicant
discloses the invention, the examiner must still show some
evidence in the prior art or present a cogent line of
reasoning as to why the claimed subject matter would have been
obvious to the skilled artisan at the time of the invention.
We are not convinced by the examiner’s line of reasoning as it
appears that the examiner’s conclusion would have been obvious
to “not load the entire cache line into the cache” in a cache
MISS situation where the data being accessed as the highest
addressed is based on appellants’ own disclosure.
The examiner attempts to bring in a reference to Chang
for the concept of not storing data into the cache memory upon
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