Appeal No. 1998-1510
Application No. 08/205,737
instruction is loading the last data word from that line for
the purpose of eliminating an unnecessary storeback for that
cache line and immediately making available for new data a
line in the cache that is no longer needed. Thus, concludes
the examiner, it would have been obvious to modify Intel to
invalidate a cache line when it is known that the cache line
will not be accessed again because the POP operation has
removed the last word from that cache line.
However, paragraph (iv)(b) of claim 1 requires the step
of
directing said processor to retrieve said read
data from said main memory without copying said read
data to said at least one cache line if said read
data is not contained within said stack cache memory
device and said read data corresponds to the highest
address word in said at least one cache line...
Thus, when there is a cache MISS on a POP read and the read
data corresponds to the highest address word, the instant
invention causes the processor to retrieve the read data from
the main memory without copying the read data to the cache
line. Neither Intel nor Baum addresses such a situation. We
agree with appellants that while Baum may describe certain
stack cache operations when there is a POP to the last word in
a cache line and there is a cache HIT, Baum is completely
4
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007