Appeal No. 1998-1895 Page 8
Application No. 08/425,990
Here, the examiner fails to identify a sufficient
suggestion to combine van der Wal with Schreiber. Schreiber
teaches "bandwidth-reduction systems ...." Col. 1, l. 9. For
its part, van der Wal discloses "multiresolution signal
processing circuitry which has been simplified so that it may
be implemented as a single IC. The circuitry includes a
filter and is configured to accept input signals having
imbedded
timing signals." Col. 2, ll. 50-54. Although van der Wal
teaches that "[i]n this configuration, multiple signal
processing circuits may be coupled in cascade to produce a
multi-stage pyramid processing system", id. at ll. 58-60, the
examiner fails to identify a sufficient suggestion to add the
multi-stage pyramid processing system to the systems of
Schreiber.
As aforementioned, the examiner relies only on certain
lines in van der Wal for a suggestion to combine van der Wal
with Schreiber. To put the lines in context, the full
paragraph of the reference that contains the lines follows.
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