Appeal No. 1998-2661
Application 08/633,267
found it obvious to therefore combine the teachings and
suggestions of the two references together as urged by the
examiner.
Since Sato is the only reference relied upon by the
examiner in this rejection which provides a basis for the
claimed virtual rename buffers, we are left with no reference
which teaches or relates to virtual rename buffers in an
instruction execution environment as recited in claims 2
through 16, 18 and 19. Therefore, we reverse the rejection of
these claims in light of the examiner's combination of Sato
and Deosaran.
On the other hand, we sustain the rejection of
independent claims 1 over Deosaran alone. We do not agree
with appellants' urgings in the brief that Deosaran does not
teach the pre-assignment of physical rename registers to an
instruction before the register is available to receive the
result of the execution of that instruction. Deosaran's
register renaming circuit RRC
in-part makes use of a variable advance instruction window
VAIW. Within Deosaran the renaming function occurs when a new
instruction enters this window. So-called tags are assigned
16
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