Ex parte WUU et al. - Page 2

          Appeal No. 1998-2887                                                        
          Application No. 08/630,111                                                  

               Claim 14 is the only independent claim on appeal, and it               
          reads as follows:                                                           
          14. A novel plug structure for stacked contacts and metal                   
          contacts on a Static Random Access Memory (SRAM) cell having                
          thin film transistors, on a partially completed semiconductor               
          substrate having device areas and field oxide areas and                     
          further having field effect transistors (FETs) and word lines               
          formed from a first polysilicon layer and Vss ground plate                  
          formed from a second polysilicon layer comprising of:                       
               a first insulating layer on said substrate;                            
               a patterned N  doped third polysilicon layer on said first+                                                         
          insulating layer forming first and second gate electrodes for               
          a first and second thin film transistor;                                    
               a second insulating layer forming a gate oxide on said                 
          first and second gate electrodes;                                           
               a patterned N type amorphous silicon layer on said second              
          insulating layer with P  doped areas over said first and+                                                    
          second gate electrodes and with undoped P  type areas for+                                  
          channel regions on said first and second thin film                          
          transistors; and                                                            
               said channel regions contiguous with said P-doped areas                
          and said P-doped areas extending over areas of the other said               
          gate electrode and on said second insulating layer;                         
               said patterned N type amorphous silicon layer having                   
          openings in said P-doped areas of said amorphous polysilicon                
          layer over said other gate electrode area and to said second                
          insulating layer;                                                           
               a third insulating layer over said patterned N type                    
          amorphous silicon layer having openings aligned over and                    
          larger in size than said openings in said P doped portions of               
          said amorphous silicon layer,                                               


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