Appeal No. 1998-2896
Application No. 08/558,564
Claims 30, 32 and 40 stand rejected under 35 U.S.C. § 103
as being unpatentable over Tamura in view of Saitoh.
Claims 31 and 33 through 36 stand rejected under 35
U.S.C.
§ 103 as being unpatentable over Tamura in view of Saitoh,
Hillenius and Wolf (Volume 2).
Claims 37 and 41 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Tamura in view of Saitoh and Wolf
(Volume 1).
Reference is made to the briefs and the answer for the
respective positions of the appellant and the examiner.
OPINION
The obviousness rejection of claims 30 through 37, 40 and
41 is reversed.
Tamura discloses a MOS semiconductor device (Figure 4D)
with a silicon substrate 31, field oxide 32, gate oxide 35,
polycrystalline silicon layer 36, insulating layer 38 and
silicide layer 39. The insulating layer 38 is located between
the polycrystalline silicon layer 36 and the silicide layer 39
in an area of the MOS device where the polycrystalline silicon
layer 36 and the silicide layer 39 are not in direct contact.
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