Appeal No. 1999-2712 Page 11
Application No. 08/165,082
Wilson teaches that high temperatures and pressures are used in the semiconductor art. However, we
are in agreement with appellants (reply brief, page 3) that “just because integrated circuits are
fabricated on a semiconductor substrate does not mean a completed or partially fabricated integrated
circuit can withstand the same temperature and pressure extremes as the substrate by itself.”
The examiner further asserts (answer, page 6) that “[t]he dielectric layer in the pending claims
could be made by any process at all, whether by sol-gel processing as disclosed, by sputtering as
taught by Koyama et al., by deposition of a thick layer of dielectric followed by etching to thin the
layer, or by wafer bonding between a semiconductor substrate and an overlying dielectric wafer.” We
find no evidence of record to support the examiner’s statement. We are cognizant of the fact that the
references to Koyama and Brandmayr together show each of the “parts” of the invention, to the extent
that Brandmayr shows a capacitor having a BST layer with a grain size of less than 100 nanometers.
However, none of the cited references applied against the claim by the examiner, nor the processes
advanced by the examiner provide a teaching that modification of the process of Koyama would have
resulted in a capacitor in an integrated circuit having a grain size of less than 200 nanometers as
claimed.
As to the issue of whether the reference to Brandmayr is analogous art, as stated by the court
in In re Oetiker, 977 F.2d 1443, 1447, 24 USPQ2d 1443, 1445 (Fed. Cir. 1992) “[i]n order to rely
on a reference as a basis for rejection of an applicant’s invention, the reference must either be in the
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