Appeal No. 1996-2702
Application No. 08/093,983
etching the second insulating film to form a side
wall insulating film on the side wall of the gate electrode
and to expose a surface of the semiconductor substrate;
forming high concentration impurity source and drain
layers in a face of the semiconductor substrate by using the
patterned gate electrode film and the side wall insulating
film as a mask;
forming a conductor film on the exposed surface of the
semiconductor substrate, the first insulating film and the
side wall insulating film;
forming a second photoresist film over the conductor
film;
patterning the second photoresist film by
photolithography to form an opening over the gate electrode;
and
etching the conductor film which is over the gate
electrode in a desired shape, using the second patterned
photoresist film as a mask.
The Examiner relies on the following prior art:
Taji 4,810,666 Mar. 07, 1989
Ku et al. (Ku) 5,010,039 Apr. 23, 1991
(filed May 15, 1989)
Favreau et al. (Favreau) 5,022,958 Jun. 11, 1991
(filed Jun. 27, 1990)
Kameyama et al. (Kameyama) 5,236,851 Aug. 17, 1993
(effectively filed Jul. 12, 1989)
Ghandhi, “Lithographic Processes,” VLSI Fabrication Principles,
pp. 534-38, 542-48 (1983).
Claims 4, 6, 7, 9, 10, and 12 stand finally rejected under
35 U.S.C. § 103. As evidence of obviousness, the Examiner offers
Taji in view of Ghandhi and Kameyama with respect to claims 7 and
3
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