Appeal No. 1996-3846
Application No. 08/251,649
BACKGROUND
The appellants’ invention relates to a dynamic random access memory (RAM)
device which uses a high impedance buffer circuit interposed between the BIMOS
differential amplifier and the bit-line pair. An understanding of the invention can be derived
from a reading of exemplary claim 1, which is reproduced below.
1. A dynamic semiconductor memory comprising:
parallel word lines provided on a substrate;
parallel bit lines provided on the substrate to insulatively cross with said word lines,
said bit lines including a bit-line pair having a first bit line and a second bit line;
memory cells connected to crossing points of said word lines and said bit lines,
said memory cells comprising voltage controlled unipolar transistors and capacitors; and
sense amplifier means connected to said bit-line pair, for sensing and amplifying a
difference between potentials on said first and second bit lines when a memory cell
connected to said bit-line pair is selected from among the memory cells in a data readout
mode, said sense amplifier means comprising a BIMOS differential amplifier circuit having
a voltage-controlled unipolar transistor and current-controlled bipolar transistors functioning
as driver elements and each of which have a base electrode;
said sense amplifier means further comprising a CMOS current mirror circuit
connected to said first and second bit lines and said base electrodes of said current-
controlled bipolar transistors.
2
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007