Appeal No. 1996-3846
Application No. 08/251,649
has not shown a teaching or provided a convincing line of reasoning to meet the limitations
of claim 1, we cannot sustain the rejection of claim 1.
With respect to claim 37, the examiner maintains that “Watanabe in figures 5 and 8
discloses a first pair (Q1, /Q1) [sic, D1, /D1] and second pair (Q3, /Q3) [sic, D3, /D3] of bit
lines, sense amplifiers (SA3) and (SA2) which selectively (using signals [blank], [blank] )
[to] prevent communication between output lines.” (See supplemental answer at page 2.)
This is a slightly different position than the examiner originally maintained in the answer at
page 4. There the examiner stated “[s]ee Figure 8 with bit lines pairs connected to
differential amplifiers SA2 whose outputs are connected in common to first and second
output lines and bipolar transistors for preventing communication.” With the original
statement of the rejection, it appears that the examiner relies upon two sense amplifiers
SA2 and using pairs of data lines D1 and D2. With this basis as the rejection, the
Appendices A and B attached to the reply brief would appear to be correct and
communication would not be prevented. The examiner has not contradicted appellants’
analysis beyond a statement that “it is not possible to selectively prevent communication
between first and second output lines.” (See supplemental answer at page 3.) This
assertion by the examiner does not address the teaching or lack of teaching of Watanabe
relative to the claimed invention. Here, the issue is not enablement or particularity of the
claimed invention, but whether Watanabe anticipated the invention as recited in claim 37.
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