Appeal No. 1998-1114
Application 08/353,254
OPINION
Appellant argues (Br8) that the combination of Yaezawa
and Wong fails to teach or suggest the limitations of claim 13
that (1) a comparator sets the RS flip-flop when the output
from the key memory and the output from the input register
coincide, and (2) the RS flip-flop turns a three-state buffer
into a high-impedance state or cancels the high-impedance
state. The Examiner breaks limitation (2) into three parts:
(2) Yaezawa does not disclose the use of a tri-state buffer;
(3) Yaezawa does not disclose controlling the tri-state buffer
with the output of the R-S flip-flop; and (4) Wong does not
disclose controlling a tri-state buffer with a flip-flop
(EA7).
We also find that the combination of Yaezawa and Wong
does not teach or suggest the input register connected to the
same terminal as a three-state buffer; however, since this
limitation is not argued, it will not be further addressed.
See 37 CFR § 1.192(c)(8)(iv) (1996) ("For each rejection under
35 U.S.C. 103, the argument shall specify the errors in the
rejection and, if appropriate, the specific limitations in the
rejected claims which are not described in the prior art
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