Appeal No. 1998-1801
Application No. 08/285,411
BACKGROUND
The invention is directed to a computer system having a set associative cache.
Claim 18 is reproduced below.
n
18. A computer system comprising a 2 way set associative cache memory
subsystem (n>0) including a data array and a corresponding address tag array,
characterized by (a) the two arrays being physically disposed in a chip boundary
crossing manner, and (b) the two arrays being accessed in a sequential manner,
when responding to a read access, and yet the two arrays function as a set
associative cache memory,
the chip boundary crossing manner comprising placing the address tag
array inside a microprocessor chip while placing the data array outside the
microprocessor chip in a single memory bank,
the sequential manner comprising accessing the on-chip address tag array
first for cache hit/miss determination and for generation of a cache address by
combining n address bits with a plurality of set and line denoting address bits in
accordance with the results of the cache hit/miss determination, and accessing only
n
one of the 2 ways of the off-chip data array subsequently using the generated
cache address.
The examiner relies on the following reference:
Moussouris et al. (Moussouris) 5,113,406 May 12, 1992
(filed Mar. 9, 1990)
Claims 18-21 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Moussouris.
We refer to the Final Rejection (Paper No. 18) and the Examiner's Answer (Paper
No. 21) for a statement of the examiner's position and to the Brief (Paper No. 20) and the
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