Appeal No. 1998-1801
Application No. 08/285,411
claimed combination of placing the address tag array inside a microprocessor chip and
the data array outside the chip. As appellants point out, Moussouris teaches that both the
tag and data array should be implemented off the CPU chip (see column 2, lines 47-56).
However, appellants appear to recognize that in the context of Moussouris’ description of
the prior art, this is merely a preferred architecture, and Moussouris may be viewed as
providing evidence that, in general, chip boundaries may be arbitrarily drawn.
n
However, appellants’ position is that in a “2 way set associative” cache memory as
presently claimed, the artisan’s knowledge of the conventional way of accessing the arrays
meant that the artisan would not have arrived at the claimed architecture of placing the
address tag array inside a microprocessor chip and the data array outside the chip.
Doing so would have been, in effect, going against the conventional wisdom.
The portion of Moussouris identified in the rejection does not appear to describe
the specifics of a set associative cache, nor the manner of accessing arrays in a set
associative cache. The examiner expresses disagreement with the assumption of
simultaneous accessing in prior art set associative cache memories. Yet, appellants point
to evidence that is argued to support their position, and the examiner has not addressed
the evidence.
Therefore, on this record, we conclude that a critical finding upon which the rejection
is based has not been established by a preponderance of the evidence. That is, the
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