Appeal No. 1998-1801
Application No. 08/285,411
examiner has failed to show there was not expectation in the prior art that the address tag
n 1
RAM and the data RAM in a 2 way set associative cache be accessed simultaneously.
The examiner further states that “as conceded by appellants, the direct
correspondence between disposition and access timing is inherent.” (Answer, page 4.)
The statement apparently refers to a sentence on page 9 of the Brief: “Note the direct
correspondence between manner of disposition and access timing levels is inherent.”
However, we do not read appellants’ “concession” as an admission relating to knowledge
that was in the prior art at the time of invention.
n
Instant claim 18 is specific as to a computer system comprising a “2 way set
associative cache memory subsystem,” with the data array and corresponding address
tag array being accessed in the defined “sequential manner,” and “accessing only one of
n
the 2 ways of the off-chip data array subsequently using the generated cache address.”
Claims 19-21, depending from claim 18, incorporate the specific requirements of claim
18. Why the detailed requirements set forth in claim 18 are deemed to have been obvious
in view of the prior art has not been satisfactorily explained. The section 103 rejection
appears based in part on Moussouris and in part on unfounded assertions regarding the
prior art.
The finding is critical to the rejection because it constitutes the Answer’s response to appellants’1
position regarding “decades of prior art practice [which] calls for accessing both arrays simultaneously,” in
the words of page 3 of the Answer.
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