Appeal No. 1998-1801
Application No. 08/285,411
cache address, and accessing only one of the “2n ways” of the data array “subsequently,”
distinguishes over the prior art.
As set forth in particular at pages 8, 11, and 12 of the Brief, appellants assert that,
in set associative caches in the prior art, tag and data arrays were simultaneously
accessed, in opposition to the “sequential manner” as defined in instant claim 18.
Appellants further argue that due to the prior art method of accessing set associative
caches, the artisan would not have been motivated to place address tag and data arrays
across chip boundaries in the manner required by instant claim 18. The examiner
responds in the Answer:
Since the purpose of the tag RAM and the data RAM are very different and
since a tag comparison must be made before any determination of the
validity of the data can be made, there seems to be little, if any actual
expectation that they be treated the same or accessed simultaneously, as
argued.
(Answer, page 4.)
Appellants quote the examiner’s statement in the Reply Brief, and refer to a
reference of record as establishing that in the prior art the tag RAM and the data RAM of a
set associative cache were expected to be accessed simultaneously. (See Reply Brief,
page 2.)
The section of Moussouris pointed out in the rejection deals with placing modules
making up cache memory architecture in various combinations with respect to chip
boundaries. The reference does not disclose, and has not been alleged to disclose, the
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