Appeal No. 1998-3130 Page 2
Application No. 08/626,174
to interconnect to a plurality of lands on the bottom surface
of the package. The lands are typically soldered to an
external PCB.
The package may also contain discrete capacitors mounted
to surface pads on the top surface of the package. The
capacitors and accompanying pads occupy valuable space on the
top of the package. Some vias must be eliminated to provide
room for the capacitors. Eliminating vias, however, reduces
the number of lands and the pin throughput of the package.
The appellants' IC package features a polygonal shaped
heat slug. The slug extends from a top surface of a package,
which has a plurality of vias. Capacitors are mounted to the
top surface of the package. Some capacitors are between the
heat slug and the vias. The polygonal shape of the heat slug
provides additional space on the top surface so that
capacitors can be added without eliminating vias from the
package.
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007