Appeal No. 1998-3326 Page 7
Application No. 08/498,819
The examiner fails to show a teaching or suggestion of
the limitations in the prior art of record. “The examiner’s
position is that the Miyazaki’s system would inherently reset
the counter.” (Paper No. 9). According to the appellants,
“[t]he Examiner indicated during an in-person interview (Paper
No. 9) that counter 24 inherently discloses a reset function.
The Examiner argued that when the 3-bit counter 24 completes a
count cycle, i.e. completes counting from 0-7, that the
counter may be viewed as inherently ‘resetting’ back to zero.”
(Appeal Br. at 9.)
For its part, Miyazaki teaches a “3-bit counter 24, which
counts the clock RMV generated by the synchronization
circuit 10.” Col. 4, l. 68, - col. 5, l. 2. Although the
counter is reset, however, it is not reset in response to an
external signal. To the contrary, the counter is reset after
reaching the state 111 when it receives the next pulse of the
clock RMV. Cf. Charles H. Roth, Fundamentals of Logic Design
268-69 (3d ed. 1085)(“Note that when the counter reaches the
state 111, the next pulse resets it to the 000 state
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