Appeal No. 1999-0045
Application 08/688,235
dependent claims within any of the above-stated rejections, including the separately stated
rejections of claim 23 identified as rejections 3 and 4 below and the rejection of claims 16-
18 and 24-26, identified as the seventh rejection, we sustain the rejection of each of these
claims as well.
At the outset, we note that each of the respective four references relied upon by the
examiner are variations upon prior art flash memory systems of the same assignee of the
present application. The examiner asserts for each of the stated rejections 1, 2, 5 and 6
argued by appellants that it would have been obvious for the artisan to have improved upon
the flash memory device of the base reference in light of the secondary and tertiary
references. We agree. Since appellants have not contested this combinability, we agree
with the examiner's reasoning for it particularly in light of the examiner's additional
embellishments provided for all rejections at pages 19-21 of the answer.
Turning to the first stated rejection relying upon Fandrich '256, we note that this
reference does not contain any particular teachings or showings of an oscillator or synch
circuit within or related to the interface circuit 40 in Figures 3 and 4a of this reference. We
embellish upon the examiner's reasoning by noting at the bottom of column 8 beginning at
line 58 that the flash memory device of Fandrich '256 may be commanded to enter a
shutdown operation to enter into a standby mode for reducing power consumption to the
extent broadly recited in the preamble of each independent claim on appeal.
Correspondingly, Fandrich '300 has significant teachings of powering up and powering
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