Appeal No. 1999-0045
Application 08/688,235
oscillator.” By implication then, the corresponding powering up operation would therefore
power up or enable the WSM oscillator.
The above-quoted portion of column 4 indicates that the clock is disabled during the
powering down operation “upon completion of programming or erasure.” Obviously, within
35 U.S.C. § 103, the artisan would have recognized that no power down operation would
have occurred unless completion of programming or erasure operations would have
occurred. Correspondingly, the disabling operations of the oscillator circuit are stated at
the end of representative claim 1 on appeal to occur when the operation, that is, a
command operation, is complete. This is consistent with the language quoted above from
column 4. These features are further developed in the entire discussion of column 5 as
well. However, the claim goes on to indicate that the disablement of the oscillator occurs
when the operation is complete “if a subsequent user command is not being received over
the host bus.” By implication, and the claims require, there will be no disablement
operation of the oscillator if subsequent user commands are received over the host bus.
Obviously, the system would not be permitted to shut down if more work was needed to be
done. All this in fact is only common sense in the art anyway as well as reasonably taught
and suggested to the artisan according to the earlier noted teachings in Fandrich '300.
The examiner's responsive arguments portion of the answer at page 15 as to this
first stated rejection again brings in the basic teaching of Fandrich '256 concerning the
existence of a queue for storing addresses and data that have been received by the flash
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