Appeal No. 1999-0045
Application 08/688,235
memory chip device in figure 3, the interface circuit of which is described in Figure 4a
which includes a data/address queue 212 and an operation queue 214, both of which are
fed by host bus 306. In the context of the overall discussion of Fandrich '300, the existence
of any remaining commands to program and/or erase within the operation queue 214
obviously would not have permitted the disablement of the oscillator circuit according to the
powering down operations identified earlier in that reference. The data including the
command structure to program and/or erase operations are fed from the common bus 306
from the host processor itself according to the earlier Figures 1 and 2 of Fandrich '256.
The conveyance of the commands from the microprocessor 999 at the bottom of Figure 1
of Fandrich '300 is stated there to be fed to the command state machine 40 and the write
state machine 48 according to the address and data buses 20 and 21 and the control
commands on buses 22-26, which obviously compare to the entire bus structure 306
Figure 1 of Fandrich '256 as well as its host bus 340 in the Figure 2 embodiment.
Turning to the second stated rejection, this rejection relies upon appellants'
admitted prior art at the top of page 2 of the specification as filed, portions of which have
been quoted at page 9 of the brief. As background to these statements, it is noted that the
admitted prior art discussion at the bottom half of page 1 of the specification as filed
indicates that user commands to prior art flash memory devices included commands for
programming and erasing operations (both transferred over a host bus (specification,
page 2, lines 12-13)) which utilized within the memory device itself specialized micro
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