Appeal No. 1999-0045
Application 08/688,235
down the so-called write state machine 48 in Figure 1 of this reference to effect power
saving operations. This amounts to another reason for combinability in addition to that
provided by the examiner. The examiner asserts, and we agree, that Fandrich '300
essentially teaches the subject matter of the last clause noted earlier with respect to
representative independent claim 1 on appeal, a feature present in each independent
claim on appeal.
Appellants' arguments with respect to the first stated rejection at pages 6-8 of the
brief are unpersuasive of patentability. The claimed commands in both references relied
upon in the first stated rejection relate to commands to program or erase data in the flash
memory itself. The timing circuitry 42 in Figure 1 of the flash memory device of Fandrich
'300 is detailed more particularly in Figure 3 and subsequent figures. As revealed in the
discussion in the paragraph bridging columns 3 and 4, it is stated at lines 8-12 of column 4
that “[t]iming circuitry 42 also clearly powers up a clock associated with write state
machine 48 and powers down the write state machine and its clock automatically upon
completion of programming or erasure.” To the extent recited in each of the claims on
appeal this directly relates to the enablement and disablement of the respective clock or
oscillator circuits of each of the independent claims on appeal. This is more specifically
recited at the bottom of column 5 where it is stated at lines 53 and 54 that the “automatic
powering down of the WSM [write state machine] 48 cleanly shuts down the WSM
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