Ex parte BOUTAND et al. - Page 2



          Appeal No. 1999-0153                                                        
          Application No. 08/488,394                                                  



          either a synchronous clock signal or an asynchronous clock                  
          signal.  The test circuitry includes two multiplexers for                   
          selecting between test signal clocks and normal function                    
          clocks.  For the portion of the circuit to be tested that uses              
          internal or synchronous signals, the first multiplexer selects              
          between the normal internal functional clock and a test clock.              
          For the portion of the tested circuit that utilizes external                
          or asynchronous clock signals, the second multiplexer selects               
          between the external clock and the output of the first                      
          multiplexer.  Appellants assert at page 81 of the                           
          specification that the described arrangement allows the                     
          internal clock signal or a test clock signal to be supplied to              
          all portions of a circuit to be tested regardless of whether                
          the circuit is normally clocked by synchronous or asynchronous              
          signals.                                                                    
          Claim 1 is illustrative of the invention and reads as                       
          follows:                                                                    
               1.  A test circuit for controlling the testing of a                    
          circuit having portions using either synchronous or                         
          asynchronous clock signals, comprising:                                     
               a first multiplexer for selectively providing as an                    
          output either said synchronous clock signal or a test clock                 

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