Appeal No. 1999-0153
Application No. 08/488,394
the language “...a circuit having portions using either
synchronous or asynchronous clock signals” appearing in the
preamble of claim 1 is broadly interpreted as meaning that all
portions of a circuit can use either synchronous or
asynchronous signals. Under this interpretation, the Examiner
asserts that the output of the multiplexer circuits can be
to a single circuit portion (as in Staiger), which single
circuit portion can use either synchronous or asynchronous
signals.
We can find no basis on the record for the Examiner
interpreting the claim language in this manner. It is
apparent to us that, when the language of the claim preamble
is read in conjunction with the language in the body of the
claim, the outputs of Appellants’ multiplexers are recited as
being applied to different portions of the tested circuit, a
concept not taught or suggested in Staiger. It is also
apparent from the Examiner’s line of reasoning in the Answer
that, since the Examiner has mistakenly interpreted the
disclosure of Staiger as disclosing the particular claimed
multiplexer outputs, the obviousness of this feature has not
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