Appeal No. 1999-0498
Application 08/532,225
apparatus for controlling instruction dispatch in a pipelined
microprocessor. More particularly, the invention is capable
of scheduling the dispatch of instructions prior to data
corresponding to a source operand being computed as a result
of the execution of another instruction.
Representative claim 1 is reproduced as follows:
1. In a pipelined microprocessor that includes a
reservation station having a plurality of entires for
buffering instructions, a method of instruction dispatch
comprising the steps of:
(a) allocating an instruction to said reservation
station in a first clock cycle of said pipelined
microprocessor;
(b) storing source operand validity information
associated with said instruction in said reservation station
during said first clock cycle whenever a source operand of
said instruction is an immediate value of an architectural
state register value;
(c) scheduling dispatch of said instruction in a
second clock cycle of said pipelined microprocessor prior to
data corresponding to said source operand being computed as a
result of the execution of another instruction.
The examiner relies on the following references:
Shebanow et al. (Shebanow) 5,355,457 Oct. 11, 1994
(filed May 21,
1991)
Nguyen et al. (Nguyen) WO 93/01545 Jan. 21, 1993
Val Popescu et al. (Popescu), “The Metaflow Architecture”,
2
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