Appeal No. 1999-0498
Application 08/532,225
same manner it stalls the processing in Shebanow and Popescu.
Each of the appealed claims recites that validity
information associated with an instruction is established
during a first clock cycle while instruction dispatch is
scheduled during a second clock cycle based on this stored
validity information and prior to data corresponding to said
source operand being computed as a result of the execution of
another instruction. Notwithstanding the examiner’s
assertions, Nguyen does not teach this recitation of the
claimed invention. Since we find that Nguyen does not support
the examiner’s findings, we are constrained to find that the
examiner has not established a prima facie case of
obviousness. Therefore, we do not sustain the examiner’s
rejection of claims 1-10, 12 and 13.
We now consider the rejection of claims 29-36. With
respect to representative, independent claim 29, the examiner
asserts the obviousness of this claim based on the collective
teachings of Popescu and Nguyen [answer, pages 5-6].
Appellants repeat their argument that neither Popescu nor
Nguyen teaches or suggests indicating the availability of a
source operand before the source operand is actually computed
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