Ex parte VAL et al. - Page 7




          Appeal No. 1999-0878                                                        
          Application 08/182,093                                                      

          420 (CCPA 1970); accord In re Pardo, 684 F.2d 912, 917,                     
          214 USPQ 673, 677 (CCPA 1982).  The fabrication of                          
          semiconductor devices is the kind of complex technology that                
          does not lend itself to Official Notice.  Neither we nor our                
          reviewing court, the U.S. Court of Appeals for the Federal                  
          Circuit, have any way of reviewing the fact asserted by the                 
          Examiner.  Even if insulating layers were well known in the                 
          semiconductor art, the Examiner provides no explanation of why              
          one skilled in the art would have been motivated to use such                
          insulating layers in Lee.  The purpose of the connector                     
          plate 80 in Lee is to provide a flexible coupling between the               
          chip contacts and the appropriate plate or signal lead                      
          (col. 6, lines 9-22), and forming the connector plate 80                    
          directly on the surface of the chip 18, as proposed by the                  
          Examiner, would be directly contrary to this purpose.                       
          Accordingly, the Examiner has failed to establish a prima                   
          facie case of obviousness of the claimed insulating layer                   
          directly coating a surface of the chip.                                     
               Furthermore, the Examiner failed to address in the final               
          rejection, and, thus, failed to establish a prima facie case                
          of obviousness of, the limitation of the metallized contact                 

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