Appeal No. 1999-1116
Application No. 08/635,170
OPINION
The examiner's statement of the rejection of instant claim 1 as being anticipated by
Machado is set forth on page 3 of the Answer. Appellant agrees with the majority of the
examiner's findings with respect to the disclosure of Machado (Brief at 4-5). Appellant
contends, however, that there is no disclosure of using a timer value, calculating a
sequencer halting point, and halting the sequencer when the sequencer operates at the
sequencer halting point, as required by claim 1.
In the initial statement of the rejection (Answer at 3), Machado's loop counter 240
(Fig. 6B) is deemed to correspond to "calculating a sequencer halting point by adding a
predetermined time constant...to the timer value." In the response to appellant's
arguments, however, the examiner (id. at 5) refers to index timeout counter 242 (Fig. 6B)
as generating an index timeout value, and refers to column 17, lines 50 through 67 of the
reference. In the Reply Brief (at 2-3), appellant disagrees with any suggestion that the
index timeout counter 242 corresponds to the claimed calculation of adding a
predetermined time constant to the timer value.
Machado discloses a sequencer 152 (Fig. 5) as an element of circuit 140. Figures
6A and 6B show details of sequencer 152. The loop counter 240 is preset with the
number of loops to be made during a particular block transfer transaction, and generates a
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