Appeal No. 1999-1116
Application No. 08/635,170
LOOPCNT=0 control value when the count reaches zero. Machado at col. 17, ll. 50-54.
Loop counter 240 is decremented by signal ISDL. See id. at Fig. 6B and col. 26. ll. 61-62.
Index timeout counter 242 (Fig. 6B) is a counter similar to loop counter 240. A
once-per-revolution index signal is used to clock the index timeout counter, and timeout
counter 242 generates an index timeout value, "INXTCNT=0." Id. at col. 17, ll. 57-63.
According to column 19, lines 25 through 29 of the reference, the index timeout count
specifies the maximum number of index pulses that may occur while sequencer 152 is
trying to complete its program.
Neither the loop counter nor the index timeout counter, however, add "a
predetermined time constant to [the] timer value," as recited in instant claim 1. The
examiner refers (Answer at 3) to column 13, line 48 of the reference as disclosing the
reading of a timer value. Machado at column 13, lines 40 through 62 describes the servo
data decoder circuit 142 (Fig. 5; an element of circuit 140) as including a "sector timer"
which puts out expected servo sector times within circuit 140 based upon detection of
each servo address mark. While the section might suggest that circuit 140 utilizes a "timer
value" and a "predetermined time constant" in a determination with respect to halting the
sequencer to prevent overrun, Machado does not expressly disclose that which is required
by instant claim 1.
The examiner contends (Answer at 5) that the "forcible halting" of the sequencer
"must involve timing, as a sequencer interrupt is only forced if enabled. The 'enable' latch
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