Appeal No. 1999-1116
Application No. 08/635,170
corresponds to the timeout limit." However, as appellant points out on page 2 of the Reply
Brief, it is unclear to what "latch" the examiner refers. Moreover, we agree with appellant
that there is no clear disclosure of steps in the operation that results in the setting of bit 0
(Machado col. 21, ll. 1-7), forcing the sequencer to halt. Considering the teachings of
Machado as a whole, it appears more likely that the sequencer is halted as a result of the
counting of block transfers and index signals, rather than as a result of a timer value
method as set forth in claim 1.
Anticipation requires the presence in a single prior art reference disclosure of each
and every element of the claimed invention, arranged as in the claim. Lindemann
Maschinenfabrik GmbH v. American Hoist & Derrick Co., 730 F.2d 1452, 1458, 221
USPQ 481, 485 (Fed. Cir. 1984). Since the Machado reference does not expressly
disclose the method of instant claim 1, and there has been no showing that the apparatus
necessarily must perform the steps required by the claim, we cannot sustain the section
102 rejection of claim 1, nor that of the claims depending therefrom.
Each of instant claims 3 and 9 requires "forcibly halting said sequencer when said
sequencer halting point is equal to said incremented timer value." The rejection (Answer
at 3-4) suffers from a similar deficiency as that applied against claim 1. While there may
be a "timer value" associated with servo data decoder circuit 142 (Machado col. 13), the
rejection fails to show how the timer value may be incremented and used in determining
the halting of the sequencer. The counters shown in Machado's Figure 6B (e.g., sequence
-5-
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