Appeal No. 1999-1576
Application No. 08/347,527
The examiner’s rejection (answer, page 3) reads as follows:
Japan ‘342 in figure 3 [sic, figure 1] discloses
a substrate having semiconductive regions 29 on active
device regions defined by trench regions 25 and planar
with trench fill material 28 in the trenches on
substrate. It would have been within the scope of one
of ordinary skill in the art to form the regions such
that they are of different thicknesses or such that
they are doped with different dopant atoms or to
different concentrations in formation of a BiCMOS
device in view of the motivation provided by Eklund to
form a BiCMOS device having regions of different
dopant types and concentrations as well as thicknesses
and the motivation provided by Jastrzebski to form
different semiconductive regions selectively by
masking regions of a substrate, growing a
semiconductive region and then masking the
semiconductive region and growing another
semiconductive region on the substrate.
We agree with the appellant that: Yoneda discloses “a
method of forming a deep insulator separation in a semiconductor
integrated circuit by forming a second groove [30] on a first
groove [25] formed on a semiconductor substrate [20], and
burying the second groove to form an interelement separating
region” (brief, page 5); Eklund discloses “the use of silicon on
insulator (“SOI”) technology for making a bipolar transistor
structure on a buried oxide layer which may be incorporated into
a method for fabricating bipolar transistors in a BiCMOS
structure” (brief, page 7); Eklund teaches away from trench
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