Appeal No. 1999-1850
Application No. 08/870,406
Claims 1-5 and 7 stand rejected under 35 U.S.C. 112, second paragraph, as being vague and
indefinite.
Claims 1, 2, 6 and 7 stand rejected under 35 U.S.C. 102(b) as anticipated by Izuhara.
Claims 3-5 stand rejected under 35 U.S.C. 103 as unpatentable over Izuhara.
Reference is made to the brief and answer for the respective positions of appellants and the
examiner.
OPINION
Turning first to the rejection under 35 U.S.C. 112, second paragraph, it is the examiner’s
position that in claim 1, lines 4-5, it is not clear whether each of the first and second subcells has
at least one transistor or whether the first and second subcells, together, include at least one
transistor.
While the language of the claim could have been clearer1, it is our view that the artisan, with
the instant specification and drawings before him/her, would have understood that each of the
first and second subcells has at least one transistor. But, even if the claim language is interpreted
as meaning that each set of a first and second subcell has “at least one transistor,” it would not be
inaccurate since the fact that each subcell has at least one transistor means that each set of first
and second subcells has at least one (viz., two) transistor. In any event, since an artisan can
1Indeed, appellants attempted to amend the claims to clarify the meaning but the
amendment was refused entry by the examiner.
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