Appeal No. 1999-1855
Application 08/738,916
that the circuit of Fig. 4 still will not provide a full
range of operation. This is because S11 of Fig. 4 would
still have the same problems disclosed with respect to
the parasitic diodes when using an "n-channel transistor"
for S8 of Fig. 3.
While the Examiner's rationale is not totally clear to
us, we do our best to address it.
It is the claimed subject matter that must be enabled.
Thus, it is the Examiner's duty to point out what language in
the claim is not enabled. The language quoted by the Examiner
in the first sentence is only found in canceled claim 1, not
the claims on appeal. As best we can determine, the Examiner
has a problem with the n-channel and p-channel limitations in
the "wherein" clause of claim 8 and in claim 23, which is why
claim 21 is not included in the rejection.
Before getting to the merits, the Examiner seems to have
an objection to the terminology of "n-channel" and
"p-substrate using an N-well process" at page 3 of the
specification and also in the claims (EA6): "This disclosure
is confusing because an 'n-type transistor' is not generally
formed from 'p-type substrate having n-type well'". We do not
see the problem. Appellant discloses a conventional N-well
CMOS formation in figure 2, which has "a p-type substrate
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