Appeal No. 1999-1855
Application 08/738,916
Anticipation
Claims 8-10
Appellant argues that claim 8 recites "wherein said
voltage generator is fabricated using p-channel enhancement
mode transistors formed in n-type wells in a grounded p-type
substrate and n-channel enhancement mode transistors formed in
said grounded p-type substrate" and these limitations are not
taught or suggested in figure 3 or the disclosure associated
with figure 3 (Br9; RBr3). It is argued that figure 3 and its
associated disclosure specifically points out why the negative
voltage generator of figure 3 cannot be fabricated in this
manner (Br9).
The Examiner's position is explained for the first time
in the examiner's answer. The Examiner finds from the
description of figure 3 that "[t]he conventional negative
voltage generator is not preferably formed in a p-substrate
using an N-well process because of the aforementioned
parasitic diodes" (emphasis added) (specification, p. 3,
lines 21-23) and that "the negative voltage generator is
conventionally implemented with a P-well CMOS process"
(emphasis added) (specification, p. 3, lines 28-30), that "one
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