Appeal No. 2000-0064
Application 08/625,241
of a single instruction, in general, involves one or more
additional bus transactions that depend on the instruction
executed. For example, the processor may read from or write to
memory to exchange data between internal registers and memory.”
We do not find any relevance in this passage to the concept of
parallel processing. The passage seems to suggest that execution
of a single instruction may require several sequential uses of
the bus to complete the execution. The examiner’s position that
this passage somehow suggests parallel processing is clearly
erroneous.
We also note that appellants do not claim to have
invented parallel processing. Parallel processing, as a general
concept, was well known in the data processing arts. We agree
with appellants, however, that the mere knowledge of parallel
processing by the artisan does not establish the obviousness of
using parallel processing in the manner specifically recited in
appellants’ claims. The examiner has failed to address the
specific question of why the parallel processing as recited in
the claimed invention would have been obvious within the meaning
of 35 U.S.C. § 103. Therefore, the examiner has failed to
establish a prima facie case of obviousness.
12
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Next
Last modified: November 3, 2007