Appeal No. 2000-0622
Application No. 08/650,894
Appellants argue (brief, page 12) that:
In Sugano et al., the TAB packages, which comprise
the resin coated chips 1a and the carrier tape 2a, are
tested following soldering to the connectors 9a. On
the other hand, the presently claimed method tests the
packages prior to placing, electrically coupling, and
then sealing the packages within the housing. With the
present method, if the packages are defective, the
costs associated with electrically coupling and sealing
the packages within the housing can be eliminated.
With Sugano et al. “the defectives can be eliminated
before the stacking” (column 23, lines 31-32).
However, defective packages can still be soldered to
the connectors 9a.
Based upon the teachings of Sugano, we agree with
appellants’ argument that Sugano does not perform tests on the
tape mounted chips prior to packaging and sealing them on the
connector housing. Sugano clearly discloses (column 23, lines
11 through 32; Figure 57) that the testing is performed after the
tape mounted chips are mounted on the connector housing. Since
the sealed housing teachings of Falanga do not cure the noted
shortcoming in the teachings of Sugano, the obviousness rejection
of claims 82 through 84, 87, 88 and 91 is reversed. The
obviousness rejections of claims 85, 86, 89 and 90 are likewise
reversed because Falanga, the well-known prior art and the
conductive epoxy teachings of Ahn do not cure the noted
shortcoming in the teachings of Sugano.
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