Appeal No. 2000-1251
Application No. 08/843,786
start-up signal (TEST) to cause the IC to enter a test mode and a
reset circuit (220) coupled to the start test mode circuit and
responsive to the test mode start-up signal (TEST) for resetting
the IC after the IC has erroneously entered a test mode during
normal operation. See Appellants' specification on page 7, lines
20-30, page 9, lines 20-24 and associated figures 1-2. The
method includes the steps of generating the test mode start-up
signal (TEST) during normal operation of the IC (1) and resetting
the IC (1) based on receipt of the test mode start-up signal
(TEST). See Appellants' specification on page 7, lines 23-30,
page 9, lines 5-24 and associated figures 1-2.
Independent claims 12 and 20 present in the application are
reproduced as follows:
12. An integrated circuit, comprising:
a start test mode circuit for generating a test mode start-
up signal to cause the integrated circuit to enter a test mode;
and
a reset circuit coupled to the start test mode circuit and
responsive to the test mode start-up signal for resetting the
integrated circuit after the integrated circuit has erroneously
entered a test mode during normal operation.
20. A method for protecting an integrated circuit against the
consequences of having erroneously entering [sic; entered] a test
mode during normal operation, in which the integrated circuit
comprises a start test mode circuit for generating a test mode
start-up signal to cause the integrated circuit to enter a test
mode, wherein the method comprises the steps of:
2
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Last modified: November 3, 2007