Appeal No. 2000-1251
Application No. 08/843,786
Upon careful review, we fail to find that the Examiner has
provided the requisite findings in Slemmer or Miyawaki of a reset
circuit responsive to a test mode start-up signal for resetting
the IC after the IC has erroneously entered a test mode during
normal operation as recited in claim 12 or the step of resetting
the IC based on receipt of the test mode start-up signal as
recited in claim 20. As Appellant correctly points out, the
reset circuit (40,46) of Slemmer completely locks out the test
mode during power-up of memory. See Abstract, column 10, lines
23-26, and column 12, lines 62-65 of Slemmer. This reset circuit
is thus not responsive to the test mode start-up signal and does
not reset the IC based upon receipt of the signal. Rather, the
reset circuit locks out or prevents entry of test mode signals
during power-up of the device.
With respect to Miyawaki, Miyawaki does teach a test mode
that involves resetting the memory. This test mode involves
sending a signal to reset the memory. However, this signal was
not erroneously entered during normal operation as recited by
claim 12. Rather, the signal to reset the memory as taught by
Miyawaki was correctly entered or desired during memory
operation. Thus, Miyawaki does not teach the limitation of a
reset circuit responsive to the test mode start-up signal for
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