Appeal No. 2000-1251
Application No. 08/843,786
OPINION
With full consideration being given the subject matter on
appeal, the Examiner's rejections and the arguments of Appellants
and Examiner, for the reasons stated infra, we reverse the
Examiner's rejections of claims 12-13 and 20-22 under 35 U.S.C.
§ 103.
We first will address the rejection of claims 12 and 20
under 35 U.S.C. § 103 as being unpatentable over Slemmer in view
of Miyawaki. The Examiner states that Slemmer includes a start
test mode circuit and a reset circuit (40,60). Examiner's
Answer, Page 3, lines 14-16. The Examiner acknowledges that
Slemmer does not discuss a reset circuit responsive to the test
mode start-up signal for resetting the IC as recited in claim 12.
Examiner's Answer, Page 3, lines 17-18. To provide a motivation
for having the reset circuit of Slemmer responsive to a test mode
start-up signal for resetting the IC, the Examiner cites
Miyawaki. The Examiner argues that Miyawaki teaches various
special modes for test evaluation known in the semiconductor
memory art, including a reset memory mode which responds to a
high voltage detection or test start-up signal. Examiner's
Answer, Page 3, lines 18-20. The Examiner then concludes that it
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