Appeal No. 2000-1259
Application 08/815,894
Dudley's Figure 3, on which the examiner specifically
relies, shows Dudley's sampled amplitude read channel, which is
similar to the Figure 1 channel in that it, too, includes a
variable gain amplifier 22, a sampler 24, a gain and timing
control circuit 28, and a discrete time sequence detector 34,
with the result that the aforementioned claim limitations read on
the Figure 3 read channel in the same way as on the Figure 1 read
channel. Although not important insofar as claim 43 is
concerned, the Figure 3 channel additionally includes a DC offset
control circuit G100.
Regarding claim 43's requirement that the timing recovery
circuit and the gain control circuit be reconfigured before the
discrete time sequence detector finishes processing the discrete
time sample values of a current sector so that the read channel
can begin acquiring an acquisition preamble of a next sector, the
examiner states that
Figure 3 of Dudley et al[.] shows the parallel pipeline
processing of gain and timing control information. See
element 28. This continual adjustment of the adaptive
device of Dudley et al[.] occurs before, during, and
after data sector detection to continuously reconfigure
the device of Dudley. See column 7, lines 43-60 of
Dudley et al.
Answer at 5-6. This argument is unconvincing because the cited
passage (reproduced below) appears to be describing the gain and
timing adjustments performed by the operation of the gain control
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