Appeal No. 2000-1259
Application 08/815,894
and timing control circuits rather than the reconfiguration of
those circuits (i.e., alteration of their operational
parameters):
The equalized sample values 32 are applied over
line 27 to decision-directed gain and timing control 28
for adjusting the amplitude of the read signal and the
frequency and phase of the sampling device 24,
respectively. Timing recovery adjusts the frequency of
sampling device 24 over line 23 in order to synchronize
the equalized samples 32 to the waveform (see
co-pending U.S. patent application Ser. No. 08/313,491
entitled "Improved Timing Recovery For Synchronous
Partial Response Recording"). Gain control adjusts the
gain of variable gain amplifier 22 over line 21. The
equalized samples Y(n) 32 are sent to a discrete time
sequence detector 34, such as a maximum likelihood (ML)
Viterbi sequence detector, to detect an estimated
binary sequence ^b(n) 33. An RLL decoder 36 decodes
the estimated binary sequence ^b(n) 33 into estimated
user data 37. In the absence of errors, the estimated
binary sequence ^b(n) 33 is equal to the recorded
binary sequence b(n) 8, and the decoded user data 37 is
equal to the recorded user data 2.
(Emphasis added.) Dudley, col. 7, ll. 43-60. Furthermore, even
assuming for the sake of argument that this passage is referring
to configuring the gain control and timing control circuits in
one way while reading the preamble and in another way while
reading the user data, it does not indicate that such
reconfiguration occurs "before the discrete time sequence
detector finishes processing the discrete time sample values of a
current sector," as required by the claim.
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