Appeal No. 2000-1259
Application 08/815,894
presumably because these control signals are not described as
changing state part way through a data interval, the examiner
does not argue that the effect of these controls signals is to
reconfigure the timing recovery circuit and the gain control
circuit before the discrete time sequence detector finishes
processing the discrete time sample values of a current sector,
as required by the claim. Instead, the examiner contends that
"Figures 1 and 2 of Petersen show controller 25 and control logic
85 controlling automatic gain control circuit 51, filter 55,
pulse detector 63, and data synchronizer 67 in a continuous,
concurrent, parallel, and, thus, a pipeline mode. See column 5,
lines 45-67, et seq. of Petersen." Answer at 5. The cited
passage in Petersen begins by stating that "[t]he controller 25
constantly monitors and commands operation of the circuit chip 29
[which includes the circuits in question] over the control bus
47." The examiner's argument is unconvincing because the
"continuous, concurrent, [and] parallel" operations to which he
refers are the functions performed by the circuits in question
during the servo burst and data intervals and thus do not
constitute reconfiguration of the timing recovery and gain
control circuits in the sense of claims 43 and 57, i.e., changing
the operating parameters of those circuits.
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